Integrated circuit memory devices are widely used in consumer and commercial applications. For example, Dynamic Random Access Memory (DRAM) devices are widely used memory devices. As is well known to those having skill in the art, a DRAM device memory cell generally includes a field effect transistor and a capacitor.
In order to increase the integration density of integrated circuit memory devices, it is generally desirable to decrease the cell area. Accordingly, for DRAMs, three-dimensional capacitor structures such as trench or stacked capacitors have been used. See, for example, U.S. Pat. No. 5,214,603 entitled Folded Bit Line, Ultra-High Density Dynamic Random Access Memory Having Access Transistors Stacked Above Storage Capacitors and U.S. Pat. No. 5,208,470 entitled Semiconductor Memory Device with a Stacked Capacitor. Stacked capacitor techniques have also been improved to further increase the surface area, for example, by providing cylindrical and fin-type capacitors. From a fabrication standpoint, DRAM devices may be classified into capacitor over bit line (COB) methods and structures wherein a capacitor is formed after forming the bit line, and capacitor under bit line (CUB) methods and structures wherein the capacitor is formed prior to forming the bit line.
Integrated circuit memory devices such as DRAM devices generally include a memory cell array region and a core and peripheral region outside the memory cell array region for logic devices and/or external input/output devices. The core and peripheral region will be referred to herein as the peripheral region.
The memory cell array region generally includes one or more arrays of memory cells. Each array generally includes a plurality of memory cells arranged in rows and columns. A plurality of generally orthogonal bit lines and word lines are employed to address individual memory cells in the array. Thus, a specified word line and a specified bit line can address a specific memory cell in a memory cell array for reading or writing. Sense amplifiers may be coupled to one or more bit lines to sense the data in a memory cell.
In order to provide high-speed integrated circuit memory devices, it is generally desirable to provide low resistance word lines and bit lines. FIG. 1 is a cross-sectional view of a conventional DRAM device wherein polycide is used as a bit line. As shown in FIG. 1, in fabricating a DRAM device, bit line wiring 10a in the cell array region and a contact plug 10b that contacts an underlying n.sup.+ -type source/drain region 16 in the peripheral region may be simultaneously formed of polysilicon. Then, after forming capacitors 18, metal lines 12 are formed to contact the p.sup.+ -type source/drain region 14, the n.sup.+ -type source/drain regions and the doped polysilicon wiring 10b. As shown in FIG. 1, the topography of the cell array region and the peripheral region may differ, causing a large step therebetween. This may make it difficult to perform photolithography for the metal lines 12a in the peripheral region. Moreover, the polysilicon wiring may provide undesirably high resistance.
In order to further reduce the wiring resistance, it is known to employ a metal bit line instead of a conventional polysilicon, silicide or polysilicon/silicide bit line. For example, U.S. Pat. No. 5,407,861 entitled Metalization over Tungsten Plug describes a plug contact process wherein contact holes are etched and an ohmic/barrier metal layer such as titanium/titanium nitride and a filler metal such as tungsten are blanket deposited. Tungsten hexaflouride (WF.sub.6) is used as a source gas for depositing the tungsten layer. The barrier metal layer is generally very thin, compared to the tungsten contact plug layer which generally is deposited to a thickness of greater than half the contact layer. In particular, the barrier metal layer may have thickness between several tens to several hundred .ANG.ngstroms. Accordingly, if the barrier metal layer does not function properly, for example due to poor step coverage, particularly at the bottom comer of a contact hole, the fluorine component of the tungsten hexaflouride gas may react with the titanium component of the barrier metal layer. As a result, an undesirable nonconductive material such as TiF.sub.x may be produced on the contact hole which can increase the contact resistance. Moreover, a lifting between the metal line and the source/drain region 16 also may take place, giving an incomplete electrical connection. Finally, depending on the process condition of the ohmic contact formation, the contact resistance between the metal material and the underlying layer also may vary.
In fabricating DRAM devices, a metal contact plug that contacts a p.sup.+ -type source/drain region in the peripheral region is generally not formed simultaneously with the bit lines and the metal contact plugs that contact the n.sup.+ -type source/drain regions in the peripheral region. This is because when tungsten is used for the bit line and the metal contact plug that contacts a source/drain region, the ohmic contact to the p.sup.+ -type source/drain region may be damaged in a subsequent high temperature annealing process. In a COB structure, a high temperature anneal may take place during later deposition of a dielectric film. In a CUB structure, a high temperature anneal may take place during formation of an interlayer dielectric film, for example in depositing and reflowing borophosphosilicate glass (BPSG).
During the high temperature annealing process, dopants such as boron in the p.sup.+ -type source/drain layer may be adsorbed into the overlying silicide layer to thereby form TiB.sub.x. This may result in loss of boron in the source/drain regions, thereby increasing the depletion width and at least partially blocking electrical tunneling between the metal lines and the source/drain regions. Moreover, if the barrier metal layer does not function properly due to, for example, poor step coverage particularly at the bottom comer of the contact hole, the fluorine in the WF.sub.6 gas that remains in the barrier layer or in the filler metal layer may react with the titanium component of the barrier metal layer. As a result, undesirable nonconductive material such as TiF.sub.x may be produced on the lower contact hole which can degrade contact resistance. For these and other reasons a metal bit line and wiring to a p.sup.+ -type source/drain region generally are not formed simultaneously.
As indicated by the above discussion, as the integration density of integrated circuit memory devices continues to increase, there continues to be a need for structures and methods that can produce low contact resistance and can reduce the optical lithography process requirements.